Method and apparatus for freeing memory

Details Method and apparatus for freeing memory Method and apparatus for freeing memory

2006-08-02

2008-08-19

Lane, Jack (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

07415583

ABSTRACT:
A method and apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and a quality indicator value related to at least a portion of the stored data block. The apparatus may include a receiver to receive at least the portion of the data block transmitted according to an error correction scheme.

REFERENCES:
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patent: 1168702 (2002-01-01), None
PCT Search Report for International Application No. PCT/US03/39105, Jun. 4, 2004.
“Performance Comparision of Hybrid-ARQ Schemes”, TSG-RAN WG1#17, Stockholm, Sweden, Oct. 20-24, 2000, Agenda Item: Adhoc#24, HSDPA, Source: Motorola, pp. 1-7.
Balachandran et al., “A Proposal for EGPRS Radio Link Control Using Link Adaption and Incremental Redundancy”, Lucent Technologies, 1999, Bell Labs Technical Journal Jul.-Sep. 1999, pp. 19-36.
TSG-RAN Working Group 1 TSGR1#17(00)1382, Sweden, Nov. 21-24, Agenda Item AH24, HSDPA, Source: Lucent Technologies Title: Asynchronous and Adaptive Incremental Redundancy (A21R) Proposal for HSDPA, Document for: Discussion and decision, pp. 1-5.

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