Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-03-09
2008-08-12
Louis-Jacques, Jacques (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
07412642
ABSTRACT:
A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bit of the segment of data may be conveyed to the receiver serially via respective single-bit lanes. The segment of data, the redundant information, and the error detecting code may be accumulated within the receiver over a plurality of clock cycles. The receiver may detect an error in the segment of data using the error detecting code. In addition, the receiver may, in response to detecting the error, regenerate the segment of data using the redundant information. Further, the receiver may determine whether a resulting regenerated bit, along with remaining bits, of the segment of data are correct using the error detecting code.
REFERENCES:
patent: 4491943 (1985-01-01), Iga et al.
patent: 5844918 (1998-12-01), Kato
patent: 6473880 (2002-10-01), Cypher
patent: 6836469 (2004-12-01), Wu
patent: 6973613 (2005-12-01), Cypher
patent: 6976194 (2005-12-01), Cypher
patent: 2004/0003339 (2004-01-01), Cypher
patent: 1 274 207 (2003-01-01), None
Notification of Transmittal of the International Search Report and The Written Opinion of the International Searching Authority or the Declaration, PCT/US2006/008791, Jul. 4, 2006.
International Search Report, PCT/US2006/008791, Jul. 4, 2006.
Written Opinion of the International Searching Authority, PCT/US2006/008791, Jul. 4, 2006.
Optical Internetworking Forum, “Very Short Reach (VSR) OC-192/STM-64 Interface Based on Parallel Optics,” Dec. 18, 2000, pp. 1-14, http://www.oiforum.com/public/document.
Chaudry M. Mujtaba K
Curran Stephen J.
Louis-Jacques Jacques
Meyertons Hood Kivlin Kower & Goetzel, P.C.
Sun Microsystems Inc.
LandOfFree
System and method for tolerating communication lane failures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for tolerating communication lane failures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for tolerating communication lane failures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4011836