DMAC to handle transfers of unknown lengths

Details DMAC to handle transfers of unknown lengths DMAC to handle transfers of unknown lengths

2006-11-28

2008-10-07

Shin, Christopher B. (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S034000, C710S308000

Reexamination Certificate

active

07433977

ABSTRACT:
A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.

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Qiao, Lufeng and Wang, Zhigong, “Design of DMA Controller for Multichannel PCI Bus Frame Engine and Data Link Manager.” Conference on Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International, Jun. 2002, pp. 1481-1485, vol. 2.
Co-pending U.S. Appl. No. 11/751,109, filed May 21, 2007.

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