Non-volatile semiconductor memory and method for...

Details Non-volatile semiconductor memory and method for... Non-volatile semiconductor memory and method for...

2006-12-08

2008-10-07

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S321000, C257SE29129

Reexamination Certificate

active

07432561

ABSTRACT:
An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

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U.S. Appl. No. 11/608,393, filed Dec. 8, 2006, Mizukami et al.
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U.S. Appl. No. 11/963,046, filed Dec. 21, 2007, Arai et al.
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U.S. Appl. No. 11/608,393, filed Dec. 8, 2006, Mizukami et al.

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