Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-23
2008-10-07
Nguyen, Hiep T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S130000
Reexamination Certificate
active
07434001
ABSTRACT:
A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members and multiple sub-cache memories corresponding to the instruction processing members. Next step is using a first instruction processing member to access a first sub-cache memory. The first instruction processing member will access the rest sub-cache memories when the first instruction processing member does not access the desired data successfully in the first instruction processing member. The first instruction processing member will access the lower level memory unit until the desired data have been accessed, when the first instruction processing member does not access the desired data successfully in the sub-memories. Then, the instruction processing member returns a result.
REFERENCES:
patent: 2004/0215883 (2004-10-01), Bamford et al.
patent: 2006/0004963 (2006-01-01), Mattina et al.
patent: 2006/0112228 (2006-05-01), Shen
patent: 2007/0143546 (2007-06-01), Narad
Nguyen Hiep T
Rosenberg , Klein & Lee
LandOfFree
Method of accessing cache memory for parallel processing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of accessing cache memory for parallel processing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of accessing cache memory for parallel processing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4000693