Electrical computers and digital processing systems: support – Synchronization of plural processors
Reexamination Certificate
2005-01-21
2008-10-14
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of plural processors
C713S400000, C713S500000
Reexamination Certificate
active
07437587
ABSTRACT:
Embodiments of the invention relate to synchronizing registers. An embodiment includes a plurality of processing cells each includes a plurality of CPUs, which run at different frequencies and each of which has an ar.itc timer register. A CPU in the fastest cell of the plurality of cells is referred to as the fast CPU. CPUs in slower cells are referred to as slow CPUs. At predetermined time intervals, slow CPUs are provided with the ar.itc value of the fast CPU to replace the values of their ar.itc. As a result, values in the ar.itc registers are synchronized without providing negative time. Other embodiments are also disclosed.
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Hewlett--Packard Development Company, L.P.
Suryawanshi Suresh K
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