Method of forming a metal interconnection line in a...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S622000, C438S624000, C257SE21507

Reexamination Certificate

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07413972

ABSTRACT:
A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of the lower metal layer, forming a barrier insulation layer covering the lower metal layer and metal oxide layer, forming an FSG insulation layer on the barrier insulation layer, forming a via contact that penetrates the FSG insulation layer so as to connect to the lower metal layer, and forming an upper metal layer electrically connected to the via contact.

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patent: 6023102 (2000-02-01), Nguyen et al.
patent: 6054380 (2000-04-01), Naik
patent: 2004/0018678 (2004-01-01), Chung et al.
patent: 2004/0137648 (2004-07-01), An
patent: 2005/0124149 (2005-06-01), Kim et al.
patent: 10-2004-0017905 (2004-03-01), None
patent: 10-2004-0108032 (2004-12-01), None

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