Address generation apparatus and operation apparatus

Details Address generation apparatus and operation apparatus Address generation apparatus and operation apparatus

2005-04-28

2008-08-26

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S220000, C365S236000

Reexamination Certificate

active

07418573

ABSTRACT:
An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter respectively, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address.

REFERENCES:
patent: 6233669 (2001-05-01), Scott et al.
patent: 2002-215388 (2002-08-01), None

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