Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-03-11
2008-08-26
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S154000, C711S159000, C711S207000
Reexamination Certificate
active
07418553
ABSTRACT:
The present invention is intended to reduce unnecessary power consumption by controlling disconnection of entries unused in a translation lookaside buffer (TLB) for a long time. In an aspect of the present invention, there is provided a method of controlling electric power consumed for a translation lookaside buffer (TLB) within a central processing device having the TLB and an entry replacement mechanism wherein the TLB includes a plurality of entries and performs translation from a logical address to a physical address and the entry replacement mechanism replaces the entries of the TLB, the method including the steps of: selecting one or more entries among the plurality of entries of the TLB in accordance with one or more predefined criteria based on an output from the entry replacement mechanism, and controlling electric power supplied to the selected entries.
REFERENCES:
patent: 6125433 (2000-09-01), Horstmann et al.
patent: 6845432 (2005-01-01), Maiyuran et al.
patent: 2002/0049918 (2002-04-01), Kaxirus et al.
patent: 1202287 (2002-05-01), None
patent: 56-35228 (1981-04-01), None
patent: 7-334423 (1995-12-01), None
patent: 9-204359 (1997-08-01), None
patent: 2000-148589 (2000-05-01), None
patent: 2002-182980 (2002-06-01), None
patent: 2003-45189 (2003-02-01), None
Jung-Hi Min, et al., “A Selectively Accessing TLB for High Performance and Lower Power Consumption”, Proceedings of the third Asia-Pacific Conference on ASICs, Aug. 6, 2002, pp. 45-48.
S. Borkar, “Design Challenge of technology scaling”, IEEE Micro, 19, 4, 1999.
C.H. Kim, “Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors”, ISLPED02, Aug. 12-14, 2002.
S. Kaxiras, “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power”, ISCA, 2001.
Japanese Office Action mailed Nov. 1, 2005.
Bragdon Reginald G.
Fujitsu Limited
Gu Shawn X
Staas & Halsey , LLP
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