Data processor with block transfer control

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S118000

Reexamination Certificate

active

07415576

ABSTRACT:
A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

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SH7750 Programming Manual, Hitachi, Ltd., published Apr. 1998, pp. 4-9, 10-128, and 10-130.

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