Memory device with delayed issuance of internal write command

Details Memory device with delayed issuance of internal write command Memory device with delayed issuance of internal write command

2007-04-09

2008-10-14

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C365S230010, C365S201000

Reexamination Certificate

active

07437527

ABSTRACT:
A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

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