Method and apparatus for creating simplified false-path...

Details Method and apparatus for creating simplified false-path... Method and apparatus for creating simplified false-path...

2006-09-14

2008-10-21

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07441217

ABSTRACT:
An apparatus for creating a simplified false-path description on a false path among paths in a target circuit extracts, from descriptions on the paths, a target path description on a target path. The apparatus judges whether the target path is a false path based on the target path description. The apparatus identifies, when it is judged that the target path is a false path, a sufficient set of elements from elements included in the target path. The settings for causing every element in the sufficient set to transmit a signal conflict. The apparatus creates the simplified false-path description on the false path by deleting, from the target path description, a description on elements that are not included in the sufficient set.

REFERENCES:
patent: 6714902 (2004-03-01), Chao et al.
patent: 7398424 (2008-07-01), Higuchi
patent: 2002/0112213 (2002-08-01), Abadir et al.
patent: 2006/0123370 (2006-06-01), Vergara-Escobar
patent: 2001-067383 (2001-03-01), None
patent: 2003-526149 (2003-09-01), None
patent: 2005-149373 (2005-06-01), None

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