Clock-independent mode register setting methods and apparatuses

Details Clock-independent mode register setting methods and apparatuses Clock-independent mode register setting methods and apparatuses

2006-07-06

2008-09-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S240000, C365S230060

Reexamination Certificate

active

07426153

ABSTRACT:
Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level. Therefore, it is possible to solve the problem of restrictions regarding the operating frequency of the mode register of the semiconductor device by performing a test mode register setting operation independent of a clock signal applied to the semiconductor device.

REFERENCES:
patent: 2004/0100853 (2004-05-01), Choi et al.
patent: 2006/0098514 (2006-05-01), Kang
patent: 1020010065910 (2001-07-01), None
patent: 1020040003562 (2004-01-01), None
patent: 1020040095892 (2004-11-01), None

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