Electrical computers and digital processing systems: multicomput – Computer-to-computer direct memory accessing
Reexamination Certificate
2003-12-11
2008-10-21
Harrell, Robert B (Department: 2142)
Electrical computers and digital processing systems: multicomput
Computer-to-computer direct memory accessing
Reexamination Certificate
active
07441006
ABSTRACT:
An RNIC implementation that performs direct data placement to memory where all segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non-aligned. The type of connection that cuts-through without accessing the reassembly buffers is referred to as a “Fast” connection because it is highly likely to be aligned, while the other type is referred to as a “Slow” connection. When a consumer establishes a connection, it specifies a connection type. The connection type can change from Fast to Slow and back. The invention reduces memory bandwidth, latency, error recovery using TCP retransmit and provides for a “graceful recovery” from an empty receive queue. The implementation also may conduct CRC validation for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement (Ack) confirming segment reception.
REFERENCES:
patent: 2002/0152327 (2002-10-01), Kagan et al.
patent: 2003/0105931 (2003-06-01), Weber et al.
patent: 2003/0145230 (2003-07-01), Chiu et al.
Biran Giora
Machulsky Zorik
Makhervaks Vadim
Goodwin Kerry B.
Harrell Robert B
Hoffman Warnick
International Business Machines - Corporation
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