Method and circuit for decoding an address of an address space

Details Method and circuit for decoding an address of an address space Method and circuit for decoding an address of an address space

2005-09-28

2008-09-16

Tsai, Henry (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

C710S009000, C710S032000, C710S040000

Reexamination Certificate

active

07426583

ABSTRACT:
Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.

REFERENCES:
patent: 6173383 (2001-01-01), Casamatta
patent: 6295579 (2001-09-01), Sukegawa et al.
patent: 2004/0044806 (2004-03-01), Moll et al.

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