Method of manufacturing wiring board

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S625000, C257S532000, C257S528000, C257S700000, C257S300000, C257SE21703, C257SE23062, C174S260000

Reexamination Certificate

active

07375022

ABSTRACT:
A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected to the semiconductor chip, and pattern wirings connected to the via wirings. The method includes: forming the electrode layers, each having one or more through holes which the via wirings pierce, and the dielectric layer, and forming the capacitor; installing the capacitor such that the capacitor opposes the pattern wirings over an insulating layer; forming one or more via holes which reach the pattern wirings from the through holes; and forming the via wiring in the via hole.

REFERENCES:
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patent: 2001/0040272 (2001-11-01), Mashino
patent: 2002/0182804 (2002-12-01), Echigo et al.
patent: 2004/0056344 (2004-03-01), Ogawa et al.
patent: 2004/0164337 (2004-08-01), Yamasaki et al.
patent: 2004/0180540 (2004-09-01), Yamasaki et al.
patent: 2006/0118907 (2006-06-01), Park
patent: 2003 264253 (2003-09-01), None
patent: 2004 14573 (2004-01-01), None
patent: 2004 152883 (2004-05-01), None
patent: 2004 281830 (2004-10-01), None

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