Memory access systems and methods for configuring ways as...

Details Memory access systems and methods for configuring ways as... Memory access systems and methods for configuring ways as...

2005-12-20

2008-05-20

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S202000, C711S118000, C711S129000, C711S173000, C365S049130, C365S230030

Reexamination Certificate

active

07376791

ABSTRACT:
A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information stored in control registers. A cache hit detection circuit includes an address register storing the data access address, tag memories storing tag data of the data access address, a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal, and address comparators each comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match. The tag data is adjusted to a predetermined address by the data processing device, which is the highest address of memory space of the processor.

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“ADSP-BF531/ADSP-BF532/ADSP-BF533” Analog Devices; 2005.

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