Layout verification method and device

Details Layout verification method and device Layout verification method and device

2005-09-13

2008-03-04

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07340701

ABSTRACT:
There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring and a wiring adjacent thereto, a calculation step of calculating an antenna ratio according to the space between the target wiring and the adjacent wiring, the area of the gate, and the area of the target wiring, and an output step of outputting an antenna damage error when the antenna ratio exceeds a predetermined value.

REFERENCES:
patent: 6713817 (2004-03-01), Kitagawa et al.
patent: 2002/0063296 (2002-05-01), Kitagawa et al.
patent: 2002/0083405 (2002-06-01), Ishikura
patent: 2002/0192886 (2002-12-01), Inoue
patent: 2001-282884 (2001-10-01), None

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