Clock control system and clock control method

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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Details

C713S320000, C713S330000, C713S340000, C713S600000

Reexamination Certificate

active

07340624

ABSTRACT:
This invention relates to a clock control system including a CPU, a peripheral functional block for the CPU, a frequency multiplication circuit which multiplies the frequency of an input system clock and outputs the multiplied system clock, a plurality of frequency division circuits which divide the frequency of a signal output from the frequency multiplication circuit to generate clocks to be supplied to the CPU and peripheral functional block, and a clock controller which changes the frequency multiplication ratio of the frequency multiplication circuit to 1/N (positive integer) and then changes the frequency division ratio of the frequency division circuit arranged on the input stage of the peripheral functional block to 1/N in order to set the CPU to a low-power consumption mode, and a method of controlling the clock control system.

REFERENCES:
patent: 5524035 (1996-06-01), Casal et al.
patent: 6346833 (2002-02-01), Kuroki
patent: 6771100 (2004-08-01), Ishimi
patent: 7000140 (2006-02-01), Okubo et al.
patent: 2000-222061 (2000-08-01), None
patent: 2000-347640 (2000-12-01), None
patent: 2000-347762 (2000-12-01), None
patent: 2001-296842 (2001-10-01), None
patent: 2002-108490 (2002-04-01), None

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