Nonvolatile memory solution using single-poly pFlash technology

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S318000, C257SE29304

Reexamination Certificate

active

07339229

ABSTRACT:
A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

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patent: 5736764 (1998-04-01), Chang
patent: 5912842 (1999-06-01), Chang et al.
patent: 6166954 (2000-12-01), Chern
patent: 6329257 (2001-12-01), Luning et al.
patent: 6788573 (2004-09-01), Choi

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