Graph pruning scheme for sensitivity analysis with partitions

Details Graph pruning scheme for sensitivity analysis with partitions Graph pruning scheme for sensitivity analysis with partitions

2006-08-31

2008-09-02

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S016000

Reexamination Certificate

active

07421671

ABSTRACT:
A method of analyzing a circuit simulation comprising pruning a signal flow graph. Pruning the signal flow graph includes selecting a current vertex from a multiple input vertices in the signal flow graph. Each one of the input vertices is connected to a primary input of the signal flow graph. Determining if the current vertex includes at least one of a sensitivity parameter or a sensitivity variable. If the current vertex includes at least one of a sensitivity parameter or a sensitivity variable then the current vertex is identified as being part of a sensitivity path and is added to a first sub-group of vertices. Pruning the signal flow graph also includes determining if any remaining non-visited neighbor vertices remain to be analyzed. If any remaining non-visited neighbor vertices remain to be analyzed then selecting a neighboring vertex and determining if the selected neighbor vertex is identified as a sensitivity path. If the selected neighbor vertex is identified as a sensitivity path, then the first sub-group of vertices are output into a final pruned signal flow graph. A system for simulating and analyzing a circuit is also disclosed.

REFERENCES:
patent: 5502645 (1996-03-01), Guerra et al.
patent: 6014505 (2000-01-01), Schorn
patent: 6243614 (2001-06-01), Anderson
patent: 6324679 (2001-11-01), Raghunathan et al.
patent: 6721924 (2004-04-01), Patra et al.
patent: 6813761 (2004-11-01), Das et al.
patent: 2003/0066037 (2003-04-01), Patra et al.
patent: 2004/0060016 (2004-03-01), Patra et al.
patent: 2005/0050497 (2005-03-01), Tetelbaum
patent: 2005/0235232 (2005-10-01), Papanikolaou et al.
patent: 2007/0057732 (2007-03-01), Chang et al.
patent: 2003087311 (2003-03-01), None
Agarwal et al., “Statistical Clock Skew analysis Considering Intra-Die Process Variations”, 2003 International Conference on Computer-Aided Design, Nov. 9-13, 2003, pp. 914-921.
Catalano et al., “Exploring the Ability of Oscillation Based Test for Testing Continuous-Time Ladder Filters”, 7th International Symposium on Quality Electronic Design, Mar. 27-29, 2006, pp. 1-6.
Deng et al., “An Exact Algorithm for the Statistical Shortest Path Problem”, Asia and South Pacific Conference on Design Automation, Jan. 24-27, 2006, pp. 965-970.
Kuo et al., “Offset Current Cancellation Based on a Multiple-Path Feedback Compensation (MPFC) Technique for Switched-Current Circuits and Systems”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, No. 4, pp. 299-309.
Xiong et al., “Criticality Computation in Parameterized Statistical Timing”, 2006 43rd ACM/IEEE Design Automation Conference, Jul. 24-28, 2006, pp. 63-68.
Glebov et al., “Delay Noise Pessimism Reduction by Logic Correlations”, IEEE/ACM International Conference on Computer Aided Design, Nov. 7-11, 2004, pp. 160-167.
Harris et al., “Statistical Clock Skew Modeling with Data Delay Variations”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, No. 6, pp. 888-898.
Neves et al., “Optimal Clock Skew Scheduling Tolerant to Process Variations”, 33rd Design Automation Conference Proceedings, Jun. 3-7, 1996, pp. 623-628.
Ohashi et al., “Statistical Schedule Length Analysis in Asynchronous Data Path Synthesis”, IEEE International Symposium on Circuits and Systems, vol. 1, May 23-26, 2005, pp. 700-703.
Pullela et al., “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design of International Circuits and Systems, vol. 16, No. 2, pp. 210-215.
Velenis et al., “A Clock Tree Topology Extraction Algorithm for Improving the Tolerance of Clock Distribution Networks to Delay Uncertainty”, 2001 IEEE International Symposium on Circuits and Systems, vol. 4, May 6-9, 2001, pp. 422-425.
Wei et al., “Clock Skew Scheduling Under Process Variations”, 7th International Symposium on Quality Electronic Design, Mar. 27-29, 2006, pp. 1-6.
NN7308804, “Computer Assisted Design of Program Test Libraries”, IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, pp. 804-807 (pages).

Affiliated with

Also associated with

Rating

Graph pruning scheme for sensitivity analysis with partitions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Graph pruning scheme for sensitivity analysis with partitions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Graph pruning scheme for sensitivity analysis with partitions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3976421