Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2006-04-07
2008-09-23
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C438S589000, C257SE21662
Reexamination Certificate
active
07427536
ABSTRACT:
A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The source/drain regions, formed in the pillar/trench sidewalls, couple the column cells serially into bitlines. The rows of the array are each coupled by a wordline. A second set of trenches separates the columns of cells.
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Ahn Kie Y.
Forbes Leonard
Leffert Jay & Polglaze P.A.
Lindsay, Jr. Walter L
Micro)n Technology, Inc.
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