Method of forming gate arrays on a partial SOI substrate

Details Method of forming gate arrays on a partial SOI substrate Method of forming gate arrays on a partial SOI substrate

2006-05-17

2008-09-09

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S225000, C438S296000, C438S412000, C438S164000, C257SE21014, C257SE21179, C257SE21429, C257SE21621

Reexamination Certificate

active

07422960

ABSTRACT:
The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

REFERENCES:
patent: 6784076 (2004-08-01), Gonzalez et al.
patent: 2005/0199932 (2005-09-01), Abbott et al.
patent: 2005/0282342 (2005-12-01), Adan
K.H. Yeo, et al; “80 nm 512M DRAM with Enhanced Data Retention Time Using Partially-Insulated . . .”; 2004 Symposium on VLSI Technology Digest of Technology; 2004 IEEE; pp. 30-31.

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