Instruction cache way prediction for jump targets

Details Instruction cache way prediction for jump targets Instruction cache way prediction for jump targets

2002-08-12

2008-07-29

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S118000, C711S125000, C711S128000, C711S123000, C711S204000, C711S213000, C711S214000, C711S215000, C711S217000, C711S218000

Reexamination Certificate

active

07406569

ABSTRACT:
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

REFERENCES:
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Powell M D et al: “Reducing Set-Associative Cache Energy Via Way-Prediction and Selective Direct-Mapping” Micro-34. Proceedings of the 34TH Annual ACM/IEEE International Symposium on Microarchitecture, Los Alamitos, CA: IEEE Comp Soc, US, Dec. 1, 2001, pp. 54-65, XP001075831.

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