Stressed field effect transistors on hybrid orientation...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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C257S627000, C257SE27108, C257SE21632, C438S199000

Reexamination Certificate

active

07405436

ABSTRACT:
A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

REFERENCES:
patent: 6995456 (2006-02-01), Nowak
patent: 7176522 (2007-02-01), Cheng et al.
patent: 2004/0195646 (2004-10-01), Yeo et al.
patent: 2004/0256700 (2004-12-01), Doris et al.
patent: 2005/0285187 (2005-12-01), Bryant et al.
patent: 1478297 (2004-02-01), None
M. Yang, et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations”, IBM Semiconductor Research and Development Center, (2003).
R. Arghavani, et la., “Stress Management in Sub-90-nm Transistor Architecture”, IEEE Transactions on Electron Devices, vol. 51, No. 10 (Oct. 2004).

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