Semiconductor device having a shaped gate electrode and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21206, C257SE29136, C257S410000

Reexamination Certificate

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07394120

ABSTRACT:
An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and elevated source and drain located above the source and drain regions. A gate length of the gate electrode at a boundary between the device isolation region and the device region is longer than the gate length at a central portion of the device region.

REFERENCES:
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patent: 5967794 (1999-10-01), Kodama
patent: 6091117 (2000-07-01), Shiozawa et al.
patent: 6144081 (2000-11-01), Hsu et al.
patent: 6278165 (2001-08-01), Oowaki et al.
patent: 6316808 (2001-11-01), Smith, III
patent: 2001/0010383 (2001-08-01), Son et al.
patent: 2002/0024107 (2002-02-01), Inaba
patent: 2002/0113277 (2002-08-01), Mehrotra et al.
patent: 2004/0241971 (2004-12-01), Wieczorek et al.
patent: 2007/0108514 (2007-05-01), Inoue et al.
Sun, et al., “Impact of Epi Facts on Deep Submicron Elevated Source/Drain MOSFET Characteristics”, IEEE Transactions on Electron Devices, vol. 45, No. 6, pp. 1377-1380, (Jun. 1998).

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