Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-03-09
2008-07-15
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S325000, C257SE29309
Reexamination Certificate
active
07400012
ABSTRACT:
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.
REFERENCES:
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4449205 (1984-05-01), Hoffman
patent: 4495219 (1985-01-01), Kato et al.
patent: 4717943 (1988-01-01), Wolf et al.
patent: 4757360 (1988-07-01), Faraone et al.
patent: 4794565 (1988-12-01), Wu et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 4939559 (1990-07-01), DiMaria et al.
patent: 5332915 (1994-07-01), Shimoji et al.
patent: 5399516 (1995-03-01), Bergendahl et al.
patent: 5445984 (1995-08-01), Hong et al.
patent: 5455792 (1995-10-01), Yi
patent: 5498558 (1996-03-01), Kapoor
patent: 5510278 (1996-04-01), Nguyen et al.
patent: 5617351 (1997-04-01), Bertin et al.
patent: 5646430 (1997-07-01), Kaya et al.
patent: 5801401 (1998-09-01), Forbes
patent: 5852306 (1998-12-01), Forbes
patent: 5923056 (1999-07-01), Lee et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6025228 (2000-02-01), Ibok et al.
patent: 6025627 (2000-02-01), Forbes et al.
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6069380 (2000-05-01), Chou et al.
patent: 6101131 (2000-08-01), Chang
patent: 6124729 (2000-09-01), Noble et al.
patent: 6127227 (2000-10-01), Lin et al.
patent: 6134175 (2000-10-01), Forbes et al.
patent: 6141238 (2000-10-01), Forbes et al.
patent: 6141248 (2000-10-01), Forbes et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6163049 (2000-12-01), Bui
patent: 6169306 (2001-01-01), Gardner et al.
patent: 6172397 (2001-01-01), Oonakado et al.
patent: 6208164 (2001-03-01), Noble et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6229175 (2001-05-01), Uchida
patent: 6238976 (2001-05-01), Noble et al.
patent: 6246606 (2001-06-01), Forbes et al.
patent: 6249020 (2001-06-01), Forbes et al.
patent: 6249460 (2001-06-01), Forbes et al.
patent: 6288419 (2001-09-01), Prall et al.
patent: 6307775 (2001-10-01), Forbes et al.
patent: 6351411 (2002-02-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes et al.
patent: 6444545 (2002-09-01), Sadd et al.
patent: 6461931 (2002-10-01), Eldridge
patent: 6541280 (2003-04-01), Kaushik et al.
patent: 6586797 (2003-07-01), Forbes et al.
patent: 6740928 (2004-05-01), Yoshii et al.
patent: 6743681 (2004-06-01), Bhattacharyya
patent: 6778441 (2004-08-01), Forbes et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6950340 (2005-09-01), Bhattacharyya
patent: 7012297 (2006-03-01), Bhattacharyya
patent: 7072223 (2006-07-01), Bhattacharyya
patent: 7250338 (2007-07-01), Bhattacharyya
patent: 2001/0013621 (2001-08-01), Nakazato
patent: 2002/0106536 (2002-08-01), Lee et al.
patent: 2003/0042527 (2003-03-01), Forbes et al.
patent: 2003/0042532 (2003-03-01), Forbes
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0043622 (2003-03-01), Forbes
patent: 2003/0043630 (2003-03-01), Forbes et al.
patent: 2003/0043632 (2003-03-01), Forbes
patent: 2003/0043633 (2003-03-01), Forbes et al.
patent: 2003/0043637 (2003-03-01), Forbes et al.
patent: 2003/0045082 (2003-03-01), Eldridge et al.
patent: 2003/0048666 (2003-03-01), Eldridge et al.
patent: 2004/0004245 (2004-01-01), Forbes et al.
patent: 2004/0004247 (2004-01-01), Forbes et al.
patent: 2004/0004859 (2004-01-01), Forbes et al.
patent: 2005/0012141 (2005-01-01), Bhattacharyya
patent: 2005/0249024 (2005-11-01), Bhattacharyya
patent: 2006/0001083 (2006-01-01), Bhattacharyya
Bhattacharyya, A. , “Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride”,ECS Technical Digest, J. Electrochem. Soc., 131(11), 691 RDP, New Orleans,(1984),469C.
De Blauwe, J. , et al., “A novel, aerosol-nanocrystal floating-gate device for non-volatile memory applications”,IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000),683-686.
Han, Kwangseok , “Characteristics of P-Channel Si Nano-Crystal Memory”,IEDM Technical Digest, International Electron Devices Meeting, (Dec. 10-13, 2000),309-312.
Inumiya, S , et al., “Conformable formation of high quality ultra-thin amorphous Ta2 O5 gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs”,IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000),649-652.
Lee, J. , et al., “Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric”,International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000),645-648.
Luan, H. , “High Quality Ta2O5 Gate Dielectrics with Tos,eq less than 10A”,IEDM, (1999),pp. 141-144.
Manchanda, L. , “High K Dielectrics for CMOS and Flash”,Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo,(1999),150-151.
Manchanda, L. , et al., “High-K Dielectrics for Giga-Scale CMOS and Non-Volatile Memory Technology”,Lucent Technologies, Bell Laboratories,(2000),1 page.
Manchanda, L. , “Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications”,IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000),23-26.
Ohba, R. , et al., “Non-Volatile Si Quantum Memory with Self-Aligned Doubly-Stacked Dots”,IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000),313-316.
Yamaguchi, Takeshi, “Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition”,Electron Devices Meeting, 2000. IEDM Technical Digest. International, (2000),19-22.
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
Tran Thien F
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