Common circuitry supporting both bit node and check node...

Details Common circuitry supporting both bit node and check node... Common circuitry supporting both bit node and check node...

2005-06-30

2008-07-01

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000, C714S794000, C714S801000, C375S341000

Reexamination Certificate

active

07395487

ABSTRACT:
Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**− (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†− (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

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