Static random access memory cell utilizing enhancement mode N-ch

Details Static random access memory cell utilizing enhancement mode N-ch Static random access memory cell utilizing enhancement mode N-ch

1997-01-21

1998-08-11

Hoang, Huan

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365210, 36518909, C11C 1100

Patent

active

057936714

ABSTRACT:
An SRAM cell for use in a microprocessor includes enhancement mode load transistors. A control or bias circuit is coupled to the gates and drains of the load transistors to appropriately bias the load transistors. The bias circuit responds to feedback from a dummy cell to appropriately bias the load transistors. The bias circuit can operate in a refresh mode, a feedback mode, a bias mode, or access mode. The bias circuit allows the SRAM cell to operate quickly, stably, and with minimal current.

REFERENCES:
patent: 5020028 (1991-05-01), Wanlass
patent: 5148390 (1992-09-01), Hsieh
patent: 5473568 (1995-12-01), Okamura

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