Tracing instruction flow in an integrated processor

Details Tracing instruction flow in an integrated processor Tracing instruction flow in an integrated processor

2004-08-25

2008-03-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C714S045000

Reexamination Certificate

active

07340564

ABSTRACT:
Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.

REFERENCES:
patent: 4357656 (1982-11-01), Saltz et al.
patent: 5636363 (1997-06-01), Bourekas et al.

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