Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2008-04-15
2008-04-15
Ngô, Ngân V. (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C257S390000, C257SE27102, C257SE21662, C257SE21671
Reexamination Certificate
active
11672251
ABSTRACT:
A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.
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Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Koburger, III Charles W.
International Business Machines - Corporation
Ngo Ngan V.
Peterson, Jr. Charles W.
Sabo, Esq. William D.
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