Apparatus and method for memory access of sharing buses

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C711S004000, C711S147000, C710S100000, C369S047380, C360S073030

Reexamination Certificate

active

10924964

ABSTRACT:
An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's defaults and firmware, wherein the address and data pins of the SDRAM and the flash memory are coupled with a same bus respectively, and SDRAM and flash memory are not accessed at the same time; a memory interface, connecting the address bus and data bus shared by the SDRAM and flash memory. The memory interface further comprises an arbiter, deciding which one of the access requests is executed according to the request priority. It is noticed that only one of the SDRAM or the flash memory can be accessed at one time.

REFERENCES:
patent: 5995709 (1999-11-01), Tsuge
patent: 6480929 (2002-11-01), Gauthier et al.
patent: 6718443 (2004-04-01), Yoshida
patent: 2003/0070049 (2003-04-01), Suzuki
patent: 2004/0062126 (2004-04-01), Takemae
Gerritsen, Armin, CISC vs. RISC, Mar. 1999, p. 1.

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