Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-05-13
2008-05-13
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S784000, C257SE23023, C228S180500
Reexamination Certificate
active
11102408
ABSTRACT:
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.
REFERENCES:
patent: 3761782 (1973-09-01), Youmans
patent: 4394712 (1983-07-01), Anthony
patent: 4710795 (1987-12-01), Nippert et al.
patent: 4897708 (1990-01-01), Clements
patent: 5229647 (1993-07-01), Gnadinger
patent: 5432999 (1995-07-01), Capps
patent: 5483741 (1996-01-01), Akram et al.
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5496775 (1996-03-01), Brooks
patent: 5852871 (1998-12-01), Khandros
patent: 5894983 (1999-04-01), Beck et al.
patent: 5931685 (1999-08-01), Hembree et al.
patent: 5990546 (1999-11-01), Igarashi et al.
patent: 6002177 (1999-12-01), Gaynes et al.
patent: 6107109 (2000-08-01), Akram et al.
patent: 6184587 (2001-02-01), Khandros et al.
patent: 6251703 (2001-06-01), Van Campenhout et al.
patent: 6294837 (2001-09-01), Akram et al.
patent: 6326689 (2001-12-01), Thomas
patent: 6380555 (2002-04-01), Hembree et al.
patent: 6395581 (2002-05-01), Choi
patent: 6400172 (2002-06-01), Akram et al.
patent: 6444576 (2002-09-01), Kong
patent: 6451624 (2002-09-01), Farnworth et al.
patent: 6501165 (2002-12-01), Farnworth et al.
patent: 6528984 (2003-03-01), Beaman et al.
patent: 6566747 (2003-05-01), Ohuchi et al.
patent: 6569762 (2003-05-01), Kong
patent: 6577013 (2003-06-01), Glenn et al.
patent: 6600221 (2003-07-01), Kimura
patent: 6605551 (2003-08-01), Wermer et al.
patent: 6620633 (2003-09-01), Hembree et al.
patent: 6620731 (2003-09-01), Farnworth et al.
patent: 6653170 (2003-11-01), Lin
patent: 6717245 (2004-04-01), Kinsman et al.
patent: 6803303 (2004-10-01), Hiatt et al.
patent: 6812549 (2004-11-01), Umetsu et al.
patent: 6828175 (2004-12-01), Wood et al.
patent: 6833613 (2004-12-01), Akram et al.
patent: 6841883 (2005-01-01), Farnworth et al.
patent: 6848177 (2005-02-01), Swann et al.
patent: 6881648 (2005-04-01), Chen et al.
patent: 6882057 (2005-04-01), Hsu
patent: 6896170 (2005-05-01), Lyn et al.
patent: 6903443 (2005-06-01), Farnworth et al.
patent: 6906418 (2005-06-01), Hiatt et al.
patent: 6908784 (2005-06-01), Farnworth et al.
patent: 6936913 (2005-08-01), Akerling et al.
patent: 6952054 (2005-10-01), Akram et al.
patent: 6964915 (2005-11-01), Farnworth et al.
patent: 6998717 (2006-02-01), Farnworth et al.
patent: 7108546 (2006-09-01), Miller et al.
patent: 2002/0017710 (2002-02-01), Kurashima et al.
patent: 2002/0117330 (2002-08-01), Eldridge et al.
patent: 2003/0230805 (2003-12-01), Noma et al.
patent: 2003/0232460 (2003-12-01), Poo et al.
patent: 2004/0235270 (2004-11-01), Noma et al.
patent: 2007/0126091 (2007-06-01), Wood et al.
patent: 2007/0138498 (2007-06-01), Zilber et al.
Ivy Wei Qin et al., “Automatic Wedge Bonding with Ribbon Wire For High Frequency Applications”, SEMICON West 2002 SEMI Technology Symposium, pp. 1-11.
International Technology Roadmap for Semiconductors, 2005 Edition, Assembly and Packaging, pp. 1-44.
Renesas, Hitachi and Renesas Technology Develop Through-Hole Electrode Technology to Enable Interconnection of Stacked Chips at Room Temperature, News Release, Jun. 1, 2005, p. 1-2.
Dr. Ning-Cheng Lee, “The Use of Solder as an Area-Array Package Interconnect”, Chip Scale Review, Sep.-Oct. 1999, pp. 1-8, Available on line: www.chipscalereview.com/issues/.
Indium Corporation of America. Product Data Sheet. “Pb-Free Solder Fabrication”, pp. 1-2, date unavailable.
Lulicke & Soffa. “Dispense/UV Cure Kit for NOSWEEP™”, advertising, 2004, pp. 1-2. Available on line: www.kns.com.
Baumeister B. William
Fulk Steven J.
Gratton Stephen A.
Micro)n Technology, Inc.
LandOfFree
Method for fabricating semiconductor components with through... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor components with through..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor components with through... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3951543