Semiconductor integrated circuit

Electronic digital logic circuitry – Interface – Supply voltage level shifting

Reexamination Certificate

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Details

C326S027000, C326S082000

Reexamination Certificate

active

11422856

ABSTRACT:
A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion includes at least one NMOS transistor having a first threshold voltage and at least one PMOS transistor having a second threshold voltage. The semiconductor integrated circuit further includes a first MOS transistor, which is connected between the virtual ground line and a ground voltage, where the first MOS transistor has the first threshold voltage and applies the ground voltage to the virtual ground line in an active state. Also included in the semiconductor integrated circuit is a controller that is connected to the first MOS transistor, where the controller applies the ground voltage to the first MOS transistor in the active state and applies a bulk voltage supplied from a bulk power line in a standby state to control a threshold voltage of the first MOS transistor.

REFERENCES:
patent: 6118328 (2000-09-01), Morikawa
patent: 6512394 (2003-01-01), Parris
patent: 6933744 (2005-08-01), Das et al.
patent: 11-214962 (1999-08-01), None
patent: 2000-183180 (2000-06-01), None
patent: 2003-0001975 (2003-01-01), None
patent: 10-2006-0022296 (2006-03-01), None
patent: 10-2006-0046759 (2006-05-01), None
patent: 10-2006-0070448 (2006-06-01), None
English language abstract of Japanese Publication No. 11-214962, Aug. 6, 1999.
English language abstract of Japanese Publication No. 2000-183180, Jun. 30, 2000.

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