Semiconductor storage device

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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C365S194000

Reexamination Certificate

active

11580061

ABSTRACT:
A semiconductor storage device has a simple control circuit that is added to a general one-port RAM. Taking a port-A clock signal as the reference, the control circuit generates a select signal that selects a port A during the period from elapse of a first predetermined time from the reference timing until a second predetermined time has elapsed and selects a port B during other periods. The control circuit generates a port-A delayed clock signal in the period in which the port A is selected. The control circuit generates a port-B delayed clock signal during the period from elapse of the second predetermined time until a third predetermined time has elapsed. The control circuit generates a conflict monitoring signal during the period from the reference timing until the second predetermined time has elapsed. When a clock signal is supplied from the port B while the conflict monitoring signal is being generated, the port-B delayed clock signal is masked while the conflict monitoring signal is being generated. After the conflict monitoring signal is stopped, the B-port delayed clock signal is generated as a port-B clock signal.

REFERENCES:
patent: 6318707 (2001-11-01), Hara et al.
patent: 6853589 (2005-02-01), Tojima et al.
patent: 7061822 (2006-06-01), Jung
patent: 2001-094986 (2001-04-01), None
patent: 2001-101861 (2001-04-01), None
patent: 2002-108690 (2002-04-01), None

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