Low contact resistance CMOS circuits and methods for their...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S199000, C438S630000, C438S649000, C438S655000

Reexamination Certificate

active

11424373

ABSTRACT:
A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.

REFERENCES:
patent: 7158401 (2007-01-01), Bhattacharyya
patent: 2003/0148563 (2003-08-01), Nishiyama
patent: 2004/0142567 (2004-07-01), Nakajima et al.
patent: 2005/0167762 (2005-08-01), Kadoshima et al.
patent: 2005/0221612 (2005-10-01), Brown et al.
patent: 2006/0017110 (2006-01-01), Adetutu et al.
patent: 2000349169 (2000-12-01), None
patent: 2002009015 (2002-01-01), None
International Search Report for International Application No. PCT/US2007/007549, mailed Aug. 22, 2007, 3 pages.

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