Semiconductor devices with contact holes self-aligned in two...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257SE21507

Reexamination Certificate

active

11481503

ABSTRACT:
A method of forming a semiconductor device can include forming a plurality of gate structure patterns including gates and first mask patterns stacked on a semiconductor substrate, the gate structure patterns being spaced apart from each other and extending in a first direction, forming a first interlayer insulating layer covering the gate structure patterns, forming a plurality of second mask patterns extending in a second direction crossing the first direction and spaced apart from each other, and etching the first interlayer insulating layer to form a contact hole, self-aligned to the first and second mask patterns, in at least one contact region defined by a neighboring pair of the first mask patterns and a neighboring pair of the second mask patterns. Related devices are also disclosed.

REFERENCES:
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patent: 7045849 (2006-05-01), Chen et al.
patent: 2004/0046189 (2004-03-01), Chu et al.
patent: 2004/0266170 (2004-12-01), Yun
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Notice to file a Response/Amendment to the Examination Report in Korean Application No. 10-2005-0060888; Date of mailing Jun. 12, 2006.
Translations of Notice to file a Response/Amendments to the Examination Report in Korean Application No. 10-2005-0060888; Date of mailing Jun. 12, 2006.

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