Method and system for reversing the effects of sequential...

Details Method and system for reversing the effects of sequential... Method and system for reversing the effects of sequential...

2008-03-25

2008-03-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11105616

ABSTRACT:
A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.

REFERENCES:
patent: 2004/0230407 (2004-11-01), Gupta et al.
Kukula et al., Computer Aided Verification, 12thInternational Conference on Computer Aided Verification, Jul. 15-19, 2000.
Moon et al., Simplifying Circuits for Formal Verification Using Parametric Reprsentation, Formal Methods in Computer-Aided Design, 2002, p. 52-69.
Yuan et al., Constraint Synthesis for Environment Modeling in Functional Verification, Design Automation Conference, Jun. 2-6, 2003.

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