Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2008-09-02
2008-09-02
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030
Reexamination Certificate
active
11635086
ABSTRACT:
The present invention provides a memory device comprising a memory array having a plurality of memory regions, and a plurality of data path access units, each data path access unit being associated with at least one memory region. Each memory region has at least one associated memory region selected such that the data path access unit used for that memory region is different to the data path access unit used for the at least one associated memory region. For each memory region, any redundant row used in place of a faulty row in that memory region is provided in the at least one associated memory region, and a storage is provided for maintaining a record identifying each faulty row and the redundant row to be used in place of that faulty row. On receipt of a read access request specifying a read address, a lookup operation is performed in both the memory region identified by that read address and the at least one associated memory region. Further, a comparison operation is performed to determine with reference to the storage whether the read address corresponds to one of the faulty rows as identified in the record. If the comparison operation determines that the read address does not correspond to one of the faulty rows, then the read data obtained from the memory region identified by the read address is output, whereas otherwise the read data obtained from the identified redundant row in the associated memory region is output.
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ARM Limited
Nixon & Vanderhye P.C.
Phan Trong
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