Soft injection rate control for buses or network-on-chip...

Details Soft injection rate control for buses or network-on-chip... Soft injection rate control for buses or network-on-chip...

2008-05-27

2008-05-27

Knoll, Clifford (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S116000

Reexamination Certificate

active

11090118

ABSTRACT:
A programmable logic device, in accordance with an embodiment of the present invention, may comprise a bus and a plurality of programmable masters configurable to interface the bus. A first portion of a memory may include configuration data operable to configure masters of the plurality, while a second portion of the memory may include access patterns to control when the different masters of the plurality may access the bus. An injection rate controller may control when a given master is to send data on the bus based on the access pattern associated with the master. A master controller may be operable to write the access patterns for the masters to the second portion of the configuration memory.

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