Method and system for providing long and short block length...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S801000, C375S302000, C375S308000, C375S309000

Reexamination Certificate

active

10971509

ABSTRACT:
An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For ⅓ rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For ¼ rate, the LDPC code has the following relevant parameters: q=135, nldpc=64,800, kldpc=nBCH=16200, kBCH=16008 (12 bit error correcting BCH). For ⅖ rate, the following parameters exist: q=108, nldpc=64800, kldpc=nBCH=25920, kBCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

REFERENCES:
patent: 6829308 (2004-12-01), Eroz et al.
patent: 6895547 (2005-05-01), Eleftheriou et al.
patent: 7000168 (2006-02-01), Kurtas et al.
patent: 7020829 (2006-03-01), Eroz et al.
patent: 2002/0051501 (2002-05-01), Demjanenko et al.
patent: 2004/0019845 (2004-01-01), Eroz et al.
patent: 2004/0054960 (2004-03-01), Eroz et al.
patent: 2004/0086059 (2004-05-01), Eroz et al.
patent: 2004/0268205 (2004-12-01), Stolpman
patent: 2005/0063484 (2005-03-01), Eroz et al.
patent: 2005/0091565 (2005-04-01), Eroz et al.
patent: 2005/0166133 (2005-07-01), Eroz et al.
patent: 2005/0262424 (2005-11-01), Tran et al.
patent: 2005/0268206 (2005-12-01), Tran et al.
patent: 1405981 (2003-03-01), None
patent: 2001-345716 (2001-12-01), None
patent: WO 01/97387 (2001-12-01), None
Nieda, Satoshi et al.; “Low-Density Parity-Check Codes for Decoding Algorithm Based on Belief Propagation”; Technical Report of IEICE; IT2003-32; Jul. 2003; The Institute of Electronics, Information and Communication Engineers.
Wadayama, Tadashi, “A Coded Modulation Scheme Based on Low Density Parity Check Codes”; IEICE Trans. Fundamentals; vol. E84-A, No. 10; Oct. 2001; Paper—Special Issue on A Special Issue of IEICE Transactions.
Le Goff, S.Y.; “Channel Capacity of Bit-Interleaved Coded Modulation Schemes Using 8-ary Signal Constellations”; Electronics Letters; IEE Stevenage; GB; vol. 38, No. 4; Feb. 14, 2002; pp. 187-189; XP006017828; ISSN: 0013-5194.
Le Goff, S.Y.; “Signal Constellations for Bit-Interleaved Coded Modulation”; IEEE Transactions on Information Theory; vol. 49, No. 1; Jan. 2003; pp. 307-313; XP002322414.
Le Goff, S.Y.; “Signalling Constellations for Power-Efficient Bit-Interleaved Coded Modulation Schemes”; IEEE Proceedings: Communications, Institution of Electrical Engineers; GB; vol. 150, No. 3; Jun. 13, 2003; pp. 141-148; XP006020428; ISSN 1350-2425.
Hou, J. et al.; “Capacity-Approaching Bandwidth-Efficient Coded Modulation Schemes Based on Low-Density Parity-Check Codes”; IEEE Transactions on Information Theory; vol. 49, No. 9; Sep. 1, 2003; pp. 2141-2155; XP002322415.
Mansour, Mohammad et al.; “Architecture-Aware Low-Density Parity-Check Codes”; Coordinated Science Laboratory, ECE Department University of Illinois at Urbana-Champaign, Urbana, IL; pp. 57-60; XP-002302868; 2003.
Selvarathinam, Anand et al.; “A Massively Scaleable Decoder Architecture for Low-Density Parity-Check Codes”; Department of Electrical Engineering, Texas A&M University, College Station, Texas; pp. 61-61; XP-002260921; 2003.
Hocevar, Dale E.; “LDPC Code Construction with Flexible Hardware Implementation”; DSP Solutions R&D Center, Texas Instruments, Dallas, Texas; pp. 2708-2712; 2003.
Eleftheriou, E. et al.; “Low-Density Parity-Check Codes for Digital Subscriber Lines”; IBM Research, Zurich Research Laboratory; Switzerland; pp. 1752-1757; 2002.
Interaction Channel for Satellite Distribution Systems; European Standard (Telecommunications Series); Digital Video Broadcasting (DVB): ETSI EN 301 790 V1.3.1 (Mar. 2003); pp. 1-110; XP-014003845.
Narayanaswami, Ravi; “Coded Modulation with Low Density Parity Check Codes”; A thesis, submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of Master of Science; Jun. 2001; pp. 1-78; XP-002271230.
Yang, Michael et al.; “Design of Efficiently Encodable Moderate-Length Irregular LDPC Codes”; Department of Electrical and Computer Engineering; The University of Arizona, Tucson, Arizona; Sep. 27, 2002; pp. 1415-1424.
Zhang, Tong et al.; “Joint Cope and Decoder Design for Implementation-Oriented (3,k)-regular LDPC Codes”; Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis; pp. 1232-1236; 2001.
Richardson, Thomas J. et al.; “Efficient Encoding of Low-Density Parity-Check Codes”; pp. 638, 656; XP-002965294; Feb. 2001.
Gallagher, R.G.; “Low Density Parity-Check Codes”; pp. 21-28; XP-000992693; Jan. 1962.
Draft ETSI EN 302 307 V1.1.1. (Jun. 2004), XP-002312174, “Digital Video Broadcasting (DVB); Second Generation Framing Structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other Broadband Satellite Applications”, pp. 1-74; Jun. 2004.
“Design of Semi-Algebraic Low-Density Parity-Check (SA-LDPC) Codes For Multilevel Coded Modulation”, Yu Yi, Jia Hou and Moon Ho Lee, Institute of Information & Communications, Chonbuk National University, ChonJu 561-756, Korea, pp. 931-934; 2003.
XP-00231-11763, LDPC Codes, Application To Next Generation Communication Systems, Dr. Lin-Nan Lee, Vice President, Hughes Network Systems, Germantown, MD 20854, Oct. 8, 2003, pp. 1-8.
Lowering the Error-Rate Floors of Moderate-Length High-Rate Irregular LDPC Codes, Michael Yang and William E. Ryan, Department of Electrical and Computer Engineering, The University of Arizona, Tucson, AZ 85721, p. 237; Jul. 2003.
XP-002311762, ASI Centro di Geodesia Spaziale, “Giuseppe Colombo”; Matera, Italy, Apr. 7, 2003, Sub-Panel 1B “Channel Coding” Spring 2003 Meeting Report@P1, Gian Paolo Calzolari , European Space Agency, ESOC, pp. 1-11.
XP-001177711, Capacity approaching Codes, Iterative Decoding Algorithms, And Their Applications, The Renaissance of Gallager's Low-Density Parity-Check Codes, Tom Richardson, Flarion Technologies, pp. 126-131. Aug. 2003.
Low-Power VLSI Decoder Architectures for LDPC Codes, Mohammad M. Mansour and Naresh R. Shanbhag, ICIMS Research Center, ECE Dept., Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 W,. Main Street, Urbana, IL 61801, pp. 284-289; Aug. 2002.
U.S. Appl. No. 60/482,107, filed Jun. 24, 2003, Eroz et al.
EPO Communication dated Oct. 21, 2005 in counterpart European patent application No. 04256629.9.
Canadian Office Communication dated Apr. 11, 2007 in counterpart Canadian patent application No. 2486048.
Japanese Office Communication dated Jan. 9, 2007 in counterpart Japanese patent application No. 2004-312709.
Korean Office Communication dated May 17, 2006 in counterpart Korean patent application No. 10-2004-86317.
USPTO Communication dated Feb. 1, 2007 in related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
EPO Communication dated Jan. 20, 2006 in European counterpart application No. 04255344.6 of related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
EPO Communication dated Dec. 13, 2006 in European counterpart application No. 04255344.6 of related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
Chinese Office Communication dated Mar. 10, 2006 in Chinese counterpart application no. 200410087494.8 of related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
Chinese Office Communication dated Aug. 24, 2007 in Chinese counterpart application No. 200410087494.8 of related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
Canadian Office Communication dated Nov. 14, 2006 in Canadian counterpart application No. 2480145 of related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
Japanese Office Communication dated Jun. 27, 2006 in Japanese counterpart application No. 2004-258552 of related U.S. Appl. No. 10/930,298 filed Aug. 31, 2004.
Korean Office

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for providing long and short block length... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for providing long and short block length..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for providing long and short block length... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3931875

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.