Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-05-06
2008-05-06
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
11015317
ABSTRACT:
An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits for the clock in the domino pipeline, ensuring that a domino data never goes to precharge, and therefore is lost before it is consumed, ensuring that the domino datapath operates at any speed below the maximum operating speed, ensuring that domino signals leaving the design through primary outputs of a static block are latched to prevent the precharge to overwrite the evaluated results, providing an optimal solution in terms of performance, area and power, defining some constraints that are checked and enforced by the downstream tools in order to guaranty the proper functionality of the design.
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Bowers Brandon
Chiang Jack
Jorgenson Lisa K.
Kubida William J.
STMicroelectronics Inc.
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