Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-05-27
2008-05-27
Lamarre, Guy J. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S791000, C714S792000, C714S795000, C375S265000, C375S341000, C375S262000
Reexamination Certificate
active
10853089
ABSTRACT:
A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced-state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced-state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.
REFERENCES:
patent: 5136593 (1992-08-01), Moon et al.
patent: 5220570 (1993-06-01), Lou et al.
patent: 5280489 (1994-01-01), Fredrickson et al.
patent: 5291523 (1994-03-01), Bergmans et al.
patent: 5844946 (1998-12-01), Nagayasu
patent: 5870433 (1999-02-01), Huber et al.
patent: 5881106 (1999-03-01), Cartier
patent: 5910968 (1999-06-01), Chouly et al.
patent: 5970104 (1999-10-01), Zhong et al.
patent: 6035006 (2000-03-01), Matui
patent: 6088404 (2000-07-01), Jekal
patent: 6201831 (2001-03-01), Agazzi et al.
patent: 6690739 (2004-02-01), Mui
patent: 2002/0083396 (2002-06-01), Azadet et al.
patent: 2005/0060633 (2005-03-01), Parhi et al.
U.S. Appl. No. 09/471,920, filed Dec. 23, 1999, Azadet et al.
U.S. Appl. No. 09/834,668, filed Apr. 13, 2001, Azadet et al.
Azadet, K., “Gigabit Ethernet Over Unshielded Twisted Pair Cables,” Bell Laboratories, Lucent Technologies, Holmdel, NJ, USA, (Jun. 10, 1999).
Bednarz et al., “Design Performance, and Extensions of the RAM-DFE Architecture,” IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1196-1201 (Mar. 1995).
Black et al., “A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder,” IEEE Journal of Solid-State Circuits, vol. 27, No. 12 (Dec. 1992).
Chevillat et al., “Decoding of Trellis-Encoded Signals in the Presence of Intersymbol Interference and Noise,” IEEE Transactions on Communications, vol. 37, No. 7 (Jul. 1989).
Cypher et al., “Generalized Trace-Back Techniques for Survivor Memory Management in the Viterbi Algorithm,” Journal of VLSI Signal Processing, 5, pp. 85-94 (1993).
Fettweis et al., “High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture,” IEEE Communications Magazine (May 1991).
Haratsch, E.F., “High-Speed VLSI Implementation of Reduced Complexity Sequence Estimation Algorithms with Applications to Gigabit Ethernet 1000Base-T,” Bell Laboratories, Lucent Technologies, Holmdel, NJ, USA, (Jun. 10, 1999).
Haratsch, E.F., “Viterbi Dectector Architectures for Magnetic Recording,” VLSI Technology, Systems, and Applications, 2003 International Symposium, pp. 239-242 (Oct. 6-8, 2003).
Parhi, K.K., “Pipelining in Algorithms with Quantizer Loops,” IEEE Transactions on Circuits and Systems, vol. 38, No. 7, pp. 745-754 (Jul. 1991).
Rizos et al., “Reduced-Complexity Sequence Detection Approaches for PR-Shaped, Coded Linear Modulations,” IEEE Global Telecommunications Conference, vol. 1, pp. 342-346 (Nov. 1997).
Agere Systems Inc.
Lamarre Guy J.
Ryan & Mason & Lewis, LLP
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