Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2008-01-29
2008-01-29
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S161000, C257S057000, C257S059000, C257SE21703, C257SE21414, C257SE21151
Reexamination Certificate
active
11616002
ABSTRACT:
Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, source/drain electrodes, pixel electrodes and etching protecting layers. The etching protective layers cover the exposed scan lines exposed by the patterned dielectric layer and the patterned semiconductor layer, and are electrically connected to the scan lines. A passivation layer is formed, and then the passivation layer over the pixel electrodes and the patterned metal layer of the pixel electrodes are removed to expose the patterned transparent conductive layer. The patterned semiconductor layer over the scan lines between the etching protective layers and the data lines is removed to expose the patterned dielectric layer over the scan lines.
REFERENCES:
patent: 6716660 (2004-04-01), Jeong et al.
patent: 2005/0242401 (2005-11-01), Cho et al.
patent: 2006/0145157 (2006-07-01), Choi et al.
Chang Li-Chung
Chueh Chia-Hui
Huang Yu-Rung
Lee Chia-Tsung
Ahmadi Mohsen
Au Optronics Corporation
Geyer Scott B.
Jianq Chyun IP Office
LandOfFree
Fabrication method for thin film transistor array substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication method for thin film transistor array substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method for thin film transistor array substrate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3925617