Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-08
2008-04-08
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10915516
ABSTRACT:
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
REFERENCES:
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4590581 (1986-05-01), Widdoes, Jr.
patent: 4635218 (1987-01-01), Widdoes, Jr.
patent: 4675646 (1987-06-01), Lauer
patent: 4688223 (1987-08-01), Motika et al.
patent: 4845712 (1989-07-01), Sanner et al.
patent: 4901259 (1990-02-01), Watkins
patent: 4937770 (1990-06-01), Samuels et al.
patent: 4937827 (1990-06-01), Beck et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5146460 (1992-09-01), Ackerman et al.
patent: 5281864 (1994-01-01), Hahn et al.
patent: 5321828 (1994-06-01), Phillips et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5369593 (1994-11-01), Papamarcos et al.
patent: 5412260 (1995-05-01), Tsui et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5537580 (1996-07-01), Giomi et al.
patent: 5546562 (1996-08-01), Patel
patent: 5560009 (1996-09-01), Lenkov et al.
patent: 5568437 (1996-10-01), Jamal
patent: 5572712 (1996-11-01), Jamal
patent: 5574388 (1996-11-01), Barbier et al.
patent: 5581742 (1996-12-01), Lin et al.
patent: 5596587 (1997-01-01), Douglas et al.
patent: 5596743 (1997-01-01), Bhat et al.
patent: 5640542 (1997-06-01), Whitsel et al.
patent: 5644515 (1997-07-01), Sample et al.
patent: 5661662 (1997-08-01), Butts et al.
patent: 5663900 (1997-09-01), Bhandari et al.
patent: 5717699 (1998-02-01), Haag et al.
patent: 5748875 (1998-05-01), Tzori
patent: 5751735 (1998-05-01), Tobin et al.
patent: 5754827 (1998-05-01), Barbier et al.
patent: 5757819 (1998-05-01), Segars
patent: 5777489 (1998-07-01), Barbier et al.
patent: 5790832 (1998-08-01), Barbier et al.
patent: 5801956 (1998-09-01), Kawamura et al.
patent: 5805859 (1998-09-01), Giramma et al.
patent: 5809037 (1998-09-01), Mathewson
patent: 5812414 (1998-09-01), Butts et al.
patent: 5812562 (1998-09-01), Baeg
patent: 5822564 (1998-10-01), Chilton et al.
patent: 5831868 (1998-11-01), Beausang et al.
patent: 5870410 (1999-02-01), Norman et al.
patent: 5905883 (1999-05-01), Kasuya
patent: 5907697 (1999-05-01), Barbier et al.
patent: 5937190 (1999-08-01), Gregory et al.
patent: 5943490 (1999-08-01), Sample
patent: 5960191 (1999-09-01), Sample et al.
patent: 5963735 (1999-10-01), Sample et al.
patent: 5991523 (1999-11-01), Williams et al.
patent: 5999725 (1999-12-01), Barbier et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6014334 (2000-01-01), Patel et al.
patent: 6021447 (2000-02-01), Szeto et al.
patent: 6026230 (2000-02-01), Lin et al.
patent: 6041176 (2000-03-01), Shiell
patent: 6057706 (2000-05-01), Barbier et al.
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6132109 (2000-10-01), Gregory et al.
patent: 6134707 (2000-10-01), Hermann et al.
patent: 6157210 (2000-12-01), Zaveri et al.
patent: 6182247 (2001-01-01), Herrmann et al.
patent: 6182268 (2001-01-01), McElvain
patent: 6188975 (2001-02-01), Gay
patent: 6212650 (2001-04-01), Guccione
patent: 6216252 (2001-04-01), Dangelo et al.
patent: 6240376 (2001-05-01), Raynaud et al.
patent: 6247147 (2001-06-01), Beenstra et al.
patent: 6263373 (2001-07-01), Cromer et al.
patent: 6286114 (2001-09-01), Veenstra et al.
patent: 6311317 (2001-10-01), Khoche et al.
patent: 6336087 (2002-01-01), Burgun et al.
patent: 6347388 (2002-02-01), Hollander
patent: 6389586 (2002-05-01), McElvain
patent: 6421813 (2002-07-01), Jeddeloh
patent: 6438735 (2002-08-01), McElvain et al.
patent: 6449762 (2002-09-01), McElvain
patent: 6510534 (2003-01-01), Nadeau-Dostie et al.
patent: 6510541 (2003-01-01), Fujiwara et al.
patent: 6513143 (2003-01-01), Bloom et al.
patent: 6567971 (2003-05-01), Banzhaf et al.
patent: 6591369 (2003-07-01), Edwards et al.
patent: 6594802 (2003-07-01), Ricchetti et al.
patent: 7065481 (2006-06-01), Schubert et al.
patent: 2002/0133794 (2002-09-01), Kanapathippillai et al.
patent: 2002/0138801 (2002-09-01), Wang et al.
patent: 2002/0144235 (2002-10-01), Simmers et al.
patent: 2002/0147939 (2002-10-01), Wenzel et al.
patent: 2002/0147951 (2002-10-01), Nadeau-Dostie et al.
patent: 2002/0177990 (2002-11-01), Sample
patent: 2002/0194543 (2002-12-01), Veenstra et al.
patent: 2003/0009715 (2003-01-01), Ricchetti et al.
patent: 2003/0023941 (2003-01-01), Wang et al.
patent: 2003/0071606 (2003-04-01), Sunter
patent: 2003/0097615 (2003-05-01), Corti et al.
patent: 2003/0106004 (2003-06-01), Ricchetti et al.
patent: 2003/0110457 (2003-06-01), Nadeau-Dostie et al.
patent: 2003/0115522 (2003-06-01), Nadeau-Dostie et al.
patent: 2003/0115568 (2003-06-01), Miller et al.
patent: 2003/0121011 (2003-06-01), Carter
patent: 2003/0126565 (2003-07-01), Aldebert et al.
patent: 2003/0146777 (2003-08-01), Nadeau-Dostie et al.
patent: 2003/0154458 (2003-08-01), Butts et al.
patent: 2004/0250231 (2004-12-01), Killian et al.
patent: 2005/0149898 (2005-07-01), Hakewill et al.
patent: 4 042 262 (1992-07-01), None
Haufe, M., et al., “Ein Debugger fuer ASIC-Prototypen”, pp. 10, DASS Dresden Germany, 2000.
Graham, P., “Logical Hardware Debuggers for FPGA-Based Systems”, PhD Thesis, Brigham Young University, Dec. 2001, pp. 266, Relevant Sections 7.2 and 7.3.
PCT International Search Report, re PCT/US 00/32543, Jun. 28, 2001.
U.S. Appl. No. 09/724,702, filed Nov. 28, 2000.
U.S. Appl. No. 09/724,840, filed Nov. 28, 2000.
U.S. Appl. No. 09/724,839, filed Nov. 28, 2000.
U.S. Appl. No. 09/724,585, filed Nov. 28, 2000.
Bulent Dervisoglu, “Design for Testability: It is time to deliver it for Time-to-Market,” Proceedings of the International Test Conference, 1999, no page.
Keshava Iyengar Satish, “Tutorial on Design For Testability (DFT): An ASIC Design Philosophy for testability from Chips to Systems,” Sixth Annual IEEE International ASIC Conference and Exhibit, 1993, no page.
Jan Liband, “Techniques for Real-Time Debugging,” Embedded Systems Programming, vol. 8, No. 4, Apr. 1995, no page.
Dr. Vinod Agarwal, “Embedded IC Test: A New Plateau for DFT,” Evaluation Engineering, vol. 38, No. 9, Sep. 1999, no page.
Stephen O'Reilly, “Debugging Drivers with Emulators and Logic Analyzers,” Embedded Systems Programming, vol. 11, No. 2, Feb. 1998, no page.
Jack G. Ganssle, “Debuggers for Modern Embedded Systems,” Embedded Systems Programming, Nov. 1998, no page.
Brent Miller, “Scan Conversion of ASICs,” Circuit Design, vol. 7, No. 2, Feb. 1990, no page.
Jerry Bauer et al., “A Reconfigurable Logic Machine for Fast Event-Driven Simulation,” Design Automation Conference Proceedings (DAC), Jun. 1998, pp. 668-671.
Synopsys, Inc., “BSD Compiler” datasheet, www.synopsys.com/products/test/bsd—ds.html, no date, no page.
Synopsys, Inc., “DFT Compiler” Next Generation 1-Pass Test Synthesis Technology Backgrounder, Apr. 2000, no page.
Cynthia Cousineau et al., “Design of a JTAG Based Run Time Reconfigurable System,” 7thIEEE Symposium on Field Programmable Custom Computing Machines, 1999, no page.
John Andrews, “An Embedded JTAG, System Test Architecture,” Proceedings of ELECTRO, 1994, no page.
Shen XuBang et al., “Design and Implementation of a JTAG Boundary-Scan Interface Controller,” Proceedings of the 2ndIEEE Asian Test Symposium, 1993, no page.
“JTAG for system emulation,” Electronic Engineering, vol. 65, No. 794, Feb. 1993, no page.
R.P. van Riessen et al., “Design and Implementation of a Hierarchical Testable Architecture using the Boundary S
Beardslee John Mark
Koch Gernot Heinrich
Poeppe Olaf
Schubert Nils Endric
Blakely , Sokoloff, Taylor & Zafman LLP
Garbowski Leigh M.
Synplicity, Inc.
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