Controller with fail-safe function

Details Controller with fail-safe function Controller with fail-safe function

2008-05-13

2008-05-13

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Reexamination Certificate

active

10408749

ABSTRACT:
A master CPU and a slave CPU for processing data supplied from a detector unit, and a timer cleared by a clear signal supplied every predetermined time period from the master CPU when the operation of the master CPU is normal and adapted for supplying a reset signal to the master CPU and the slave CPU after the lapse of the predetermined time period and further after the lapse of another predetermined time period when an anomaly occurs in the operation of the master CPU. The master CPU monitors the processing data outputted from the slave CPU, and supplies a forced reset signal to the slave CPU when anomaly in the operation of the slave CPU is detected.

REFERENCES:
patent: 4412280 (1983-10-01), Murphy et al.
patent: 4803682 (1989-02-01), Hara et al.
patent: 5535405 (1996-07-01), Byers et al.
patent: 5870301 (1999-02-01), Yakushiji et al.
patent: 5951683 (1999-09-01), Yuuki et al.
patent: 6073249 (2000-06-01), Watabe et al.
patent: 6920520 (2005-07-01), Chen et al.
patent: 58-146907 (1983-09-01), None
patent: H06-219310 (1994-08-01), None
patent: H07-293320 (1995-11-01), None
European Search Report for corresponding European Patent Application Serial No. 03007913.1-1225 dated Aug. 16, 2007.

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