Locking-status judging circuit for digital PLL circuit

Details Locking-status judging circuit for digital PLL circuit Locking-status judging circuit for digital PLL circuit

2008-05-13

2008-05-13

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C327S156000

Reexamination Certificate

active

11091530

ABSTRACT:
A locking-status judging circuit is composed of a comparator that compares a phase error signal with a reference signal for judging whether or not a digital PLL circuit locks on an input signal and outputs a signal “0 (zero)” or a signal “1 (one)”, a selector that outputs a positive or negative number in response to the inputted signal whether it is “0” or “1”, a limiter that limits an accumulated number to be within a range of prescribed upper and lower limits, a feedback section that returns the accumulated number, an accumulator that adds the accumulated number and a positive or negative number from the selector and outputs a newly accumulated number, and a lock-state judging section that judges the digital PLL circuit whether it is in a lock-state or an unlock-state in response to an accumulated value of the newly accumulated number whether it is positive or negative.

REFERENCES:
patent: 5740205 (1998-04-01), Baum et al.
patent: 6803828 (2004-10-01), Tan et al.
patent: 6912012 (2005-06-01), Renner et al.
patent: 2002/0061087 (2002-05-01), Williams
patent: 2007/0164835 (2007-07-01), Co
patent: 3028955 (2000-04-01), None
patent: 2002-358739 (2002-12-01), None

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