Multi-gate offset source and drain field effect transistors and

Details Multi-gate offset source and drain field effect transistors and Multi-gate offset source and drain field effect transistors and

1996-07-31

1998-08-11

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257270, 257347, 257365, 257315, H01L 29788

Patent

active

057930589

ABSTRACT:
A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.

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Park et al., "Self-Aligned Offset Gated Poly-Si TFTs by Employing a Photo Resistor Reflow Process", Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials, Osaka, 1995, pp. 656-658.

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