Chip structure and chip package structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond

Reexamination Certificate

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C257S781000

Reexamination Certificate

active

11306160

ABSTRACT:
A chip structure including a chip, a passivation layer, an elastic layer and a metal layer is provided, with a bump disposed on the metal layer for electrically connecting a bonding pad of the chip. The passivation layer and the elastic layer are covering an active surface of the chip, and have an opening respectively for exposing top surface of the bonding pad, wherein the elastic layer is utilized to make the bump being heat-pressed onto a contact of a substrate with an enhanced electrical performance, and the elastic layer is made of for example polyimide or other macromolecule polymer. Moreover, the chip structure further includes a plurality of elastic granular structures at the bottom of the bump to enhance the bonding reliability of the bump.

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patent: 1683960 (2005-10-01), None

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