Semiconductor memory device having sub bit lines

Details Semiconductor memory device having sub bit lines Semiconductor memory device having sub bit lines

1988-04-18

1990-04-24

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365 51, G11C 700

Patent

active

049205170

ABSTRACT:
A dynamic random access memory which includes a memory cell array, sense amplifiers disposed at both side of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines are coupled to data busses through middle amplifiers. By use of such memory architecture, higher integration of DRAM can be realized. Also, handling of super large bit data more than 1024 bit becomes possible.

REFERENCES:
patent: 4700328 (1987-10-01), Burghard

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